Computer designers are always searching for faster memory devices that will allow them to design faster computers. A significant limitation on a computer's operating speed is the time required to transfer data between a processor and a memory circuit, such as a read or write data transfer. Memory circuits, such as a dynamic random access memories (DRAMs), usually include a large number of memory cells arranged in one or more arrays, each having rows and columns. The memory cells provide locations at which the processor can store and retrieve data. The more quickly the processor can store and retrieve data, the more quickly it can perform a calculation or execute a program using the data.
Multiport DRAMs, such as VRAMs (video random access memories), may also include a serial access memory (SAM) which permits rapid serial access to blocks of stored data. This can be particularly convenient in video applications where address sequences are often predetermined. Data is often transferred between the SAM memory cells and DRAM memory cells. FIG. 1 depicts a portion of a typical prior art multiport DRAM 10. A DRAM memory cell 12 is connected to a column or digit line D and a row or word line W. A complimentary digit line D* connects to other DRAM memory cells (not shown) that are accessed by other word lines (not shown). A SAM memory cell 14 is connected to a transfer digit line TD and to a complementary transfer digit line TD*.
Transfer transistors 18 receive a gate signal TRAN and control transfer operations between the SAM cell 14 and the digit lines D and D*. Isolation transistors 20 receive a gate signal ISO and control connection of the digit lines D and D* to sense amp circuitry 16 which senses and amplifies the voltage between the digit line pair D and D*. Access between the sense amp circuitry 16 and a DRAM I/O path I/O, I/O* is controlled by column select transistors 24 which receive a gate signal CS. Access between the SAM cell 14 and a SAM I/O path SI/O, SI/O* is controlled by column select transistors 26 which receive a gate signal SCS. When the DRAM cell 12 is not being accessed, equalization circuitry 22 provides a precharged and equalized potential of V.sub.cc /2 (where V.sub.cc is the supply voltage) to the digit line pair D and D* in response to a signal EQ. A similar transfer equalization circuit (not shown) provides a precharged and equalized potential of V.sub.cc /2 to the transfer digit line pair TD and TD*. The supply voltage V.sub.cc may be provided by an external source or by an on-chip regulator internal to the memory device, as is well known in the art.
The DRAM memory cell 12 includes an access transistor T and a data storage capacitor C. Activation of the word line W enables the access transistor T and connects the digit line D through the access transistor T to one node (the data storage node) of the capacitor C. The other node of the capacitor C is connected to a common cell plate shared by other storage capacitors of other DRAM memory cells (not shown) and is held at approximate potential V.sub.cc /2. A "1" is stored in the memory cell 12 when the storage node of the capacitor C is charged to a voltage of V.sub.cc through the access transistor T. Similarly, a "0" is stored in the memory cell 12 when the storage node of the capacitor C is charged to a voltage of V.sub.ss (usually ground potential).
As is well known, the sense amp circuitry 16 typically includes an N-sense amp (not shown) which is activated by signal NSA and functions to pull which ever of the lines D and D* is at lower potential down to ground potential. Alternatively, the N-sense amp is always activated, and the isolation transistors 20 serve to control when the function of the N-sense amp is applied to the digit line pair D and D*. The sense amp circuitry 16 further includes a P-sense amp (not shown) which is activated by signal PSA* and functions to pull which ever of the lines D and D* is at higher potential up to supply potential V.sub.cc.
FIG. 2 depicts a portion of a read-write cycle in a DRAM, whether in a memory device that is itself a DRAM or in the DRAM part of the prior art multiport DRAM device 10 of FIG. 1. Examples of a read-write cycle are the well known read-modify-write and late-write cycles. In a read-modify-write cycle, the data content of the DRAM cell 12 is transferred to external control and processing circuitry via the DRAM I/O path I/O, I/O*, and new data is transferred from the external control and processing circuitry to the DRAM cell 12 immediately thereafter. A late-write cycle differs from a read-modify-write cycle primarily in that data output buffers (not shown) are never enabled and the "read" data is not made available to the external circuitry. FIG. 2 depicts the situation in a read-write cycle in which the data to be written to the DRAM cell 12 is of the opposite state to that previously stored and read. The writing of opposite state data represents the worst case timing scenario, because of increased time necessary to develop signals and "flip"the digit lines D and D*.
Referring both to FIG. 1 and the timing diagram of FIG. 2, a DRAM read-write cycle will now be described. In response to a falling edge of a RAS* (row address strobe) signal produced by the external control circuitry (not shown), the equalization signal EQ first goes low and disengages the equalization circuitry 22 from the digit line pair D and D*. Subsequently, the word line W is activated and access is provided through transistor T to the data storage contents of capacitor C of the DRAM cell 12. As depicted in FIG. 2, the data contents in the DRAM cell was a "1", and hence the potential of digit line D rises slightly. The sense amp circuitry 16 is then activated by signals NSA and PSA*, and the potential of digit lines D and D* are pulled towards V.sub.cc and ground, respectively. In the event of a read-modify-write cycle, the column select transistors are turned on and the data is made available to the external processor via the DRAM I/O path I/O, I/O*. If, instead, the read-write cycle is a late-write cycle, data output buffers (not shown) remain disabled and the internally "read" data is not made available to the external control and processing circuitry.
A write signal pulse WRITE indicates that new data content is to be stored in the DRAM cell 12 from which data was just read. Data made available on the DRAM I/O path I/O, I/O* is transferred through the activated column select transistors 24 to the digit lines D and D*. When sufficient time has elapsed to ensure that the desired data value has been stored on the storage capacitor C of the DRAM cell 12, the word line W is shut down and the access transistor T is turned off, thereby disconnecting the digit line D from the data storage capacitor C. Subsequently, the sense amp 16 is disengaged and the equalization circuit 22 is once again engaged to equilibrate the paired digit lines D and D* to potential V.sub.cc /2.
Alternatively, FIG. 2 depicts a write transfer operation from the SAM cell 14 to the DRAM cell 12. Instead of the WRITE pulse, a write transfer pulse TRAN activates transfer transistors 18 connecting the transfer digit line pair TD and TD* to the digit line pair D and D*, and data is transferred from the SAM cell to the DRAM cell. As depicted in FIG. 2, the data transferred from the SAM cell 14 is the opposite state of that previously stored in the DRAM cell 12, and data of value "0" is now written to the storage capacitor C of the DRAM cell. Only when sufficient time has elapsed to ensure that the desired data value has been stored on the storage capacitor C of the DRAM cell 12, can the word line W be shut down and the access transistor T turned off.
Crucial to proper timing of the above-described sequences, is accurately determining when the word line W can be shut down. A premature shut down of the word line W results in potentially inaccurate data storage values, whereas shutting down the word line too late wastes time that is precious in today's high speed data transfer operations. Prior art solutions to the timing problem have generally chosen the latter course--being certain of successful data storage but at the price of wasted time.
In typical DRAM design, timing decisions are made by sensing signal development in "model" circuits. Generally, direct sensing of the actual data storage and transfer circuits themselves is undesirable because of the resulting interference with circuit performance. The crudest model implemented to address the above-described timing problem is simply an RC circuit. More sophisticated models include modeled digit lines and word lines with model memory cells and model sense amps. Signals from these models are then input to one or more delay gates and/or logic gates, and the outputs of these gates are used to control system timing. However, current methods of model signal sensing and control are sufficiently imprecise that a continued time penalty has been paid to ensure correct data storage.
The problem left incompletely solved by the prior art has been described above in terms of a read-write cycle in a DRAM or a write transfer operation in a multiport DRAM in which the data state to be written is opposite to the data having been previously stored. Those versed in the art will appreciate that the same timing problem associated with accurately and precisely shutting down the word line in the above-described sequences also occurs in other data operations, including refresh cycles in a DRAM.